Wafer-Level Low Frequency Noise Measurement Challenges and Solutions

This webinar will cover key aspects of these measurement challenges, and interpret the key specifications of a practical noise system. Attendees will understand how to evaluate real system capabilities and much more.

Accurate wafer-level measurements of low frequency noises, i.e., 1/f noise or flicker noise, random telegraph noise (RTN), thermal noise, are very challenging and users often get inaccurate or suspicious data from a measurement system. With the increasing impact and importance of those noise components to advanced device and material research, technology development, and integrated circuit designs, it is essential for researchers and engineers in the related fields to understand the real challenges and the practical solutions for wafer-level noise measurement. Accuracy, resolution, bandwidth, current and voltage biasing range, DUT impedance matching, and measurement efficiency are among the most critical aspects of a noise system.

This webinar will go through all the key aspects of these measurement challenges, and interpret the key specifications of a practical noise system, that helps audience understand how to evaluate real system capabilities, how to achieve the best wafer level resolution and bandwidth, how fast one measurement can go, how high and low current/voltage a system can measure, etc. It showcases the industry’s de-facto golden noise system that covers all these measurement needs, with unique measurement capabilities for vertical BJT, parallel noise measurement, and noise measurement with prober card. It also demonstrates wafer-level measurement data for some special conditions, e.g., high voltage, ultra-low current, high temperature, and cryogenic conditions. The speaker has over 30-year experiences in flicker noise measurement for semiconductor devices and designed multiple systems that have been the flicker noise measurement standards in foundries and leading semiconductor companies.

PRESENTER:
 

 

Dr. Zhihong Liu, CEO, ProPlus Design Solutions, Inc.

Dr. Zhihong Liu currently serves as the Chairman and Chief Executive Officer of ProPlus Design Solutions, Inc. He was most recently the Corporate Vice President for CSV R&D at Cadence Design Systems Inc. Dr. Liu co-founded BTA Technology Inc. in 1993 and invented BSIMPro, the world’s most leading Spice modeling product. He also served as the President & CEO of BTA Technology Inc. and later Celestry Design Technology Inc., which was acquired by Cadence in 2003. 

Dr. Liu holds a Ph.D. degree in EE from the University of Hong Kong and co-developed the industry’s first standard model (BSIM3) for IC designs as one of the main contributors at the University of California at Berkeley.

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Source: IEEE Semiconductors