PAM4 Demands Accurate S-parameters

PAM4 challenges signal integrity, test, and design engineers who are responsible for SERDES (serializer/deserializer) components, interconnects, backplanes, cables, connectors, circuits, and complete systems. As high speed serial data rates advance from 15 Gb/s to beyond 50 Gb/s, we face a fundamental shift. Conventional logic-emulating NRZ (Non-Return to-Zero) signaling is being…