Each year, at least 50% of tapeouts are late, with physical and circuit verification closure a significant contributing factor. Mentor incorporated the know-how of our industry-leading Calibre nmLVS sign-off tool with lessons learned from customers to create an innovative smart engine specifically engineered to help design teams find and fix high-impact systemic errors early in the design flow. As part of our growing suite of early-stage design verification technologies, the Calibre nmLVS-Recon tool enables designers to accelerate early-stage design analysis and debug cycles, and reduce the time needed to reach tapeout. We explain the concept behind our innovative technology, and introduce the first Calibre nmLVS-Recon use model – short isolation analysis.
Source: IEEE Semiconductors