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How can smartphones safely use encrypted, cloud-stored data that’s in an untrusted environment, while still preserving battery life?

One research team in the U.S. has a suggestion. They’ve developed a novel hardware accelerator prototype for edge devices that can encrypt messages going to and from the cloud with 1,000 to 6,000 times more energy efficiency than a standard RISC-V processor. They describe their proposed approach, called RISE, in a study published in the October print issue of IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

“It’s crucial to keep data encrypted at all times, even during processing. … We proposed RISE to address these issues.”
—Zahra Azad, University of Rochester

Smartphones, IoT sensors, wearable gadgets, and other edge devices tend to have limited computational capabilities and memory, so they must often send data to the cloud for processing. The exchange of data between edge devices and the cloud poses security and privacy risks, however. Even if edge devices dedicate extra computing power to encrypt data before sending it to the cloud, the data often must be decrypted in the cloud for processing.

“In certain applications, especially in the context of privacy and security, it’s crucial to keep data encrypted at all times, even during processing,” explains Zahra Azad, a postdoctoral associate at the University of Rochester.

A solution to overcome this security concern is called homomorphic encryption (HE), a cryptographic technique that allows encrypted data to be processed without decrypting it first. But homomorphic encryption comes at a cost for edge devices. “These edge-side operations lead to substantial memory consumption and impose a considerable computational overhead,” says Azad. “We proposed RISE to address these issues.”

RISE, she says, is an area- and energy-efficient hardware accelerator designed to facilitate homomorphic encryption applications on edge devices. To create RISE, Azad says she and her colleagues identified several key areas where edge devices typically experience bottlenecks in homomorphic computations. This prompted them to design RISE with three goals in mind: to share hardware for both encryption and decryption, to optimize memory access patterns (which minimizes memory needed to store the data on the accelerator chip), and to improve the chip’s error-sampling capability.

The researchers integrated RISE onto a RISC-V core and put it to the test, comparing its performance against state-of-the-art homomorphic encryption designs/solutions for the edge devices.

Homomorphic encryption, illustrated here, involves processing encrypted data without ever needing to decrypt it at the end-user’s device.

The results show that RISE outperforms its competition while maintaining the smallest memory footprint and energy consumption. Notably, Azad says, RISE can encrypt data with nearly 1/6,000th the energy consumption as a baseline processor, while it can decrypt data with some 1/1,100th the energy use. As well, RISE shows substantial improvement in latency, with less than one-percent latency rate for encrypting data and nearly 1/50th the latency for decryption.

“These results highlight RISE’s efficiency, positioning it as a promising solution for homomorphic encryption edge-side operations, particularly in situations where low latency, low area, and energy efficiency are essential,” says Azad.

She notes that while RISE offers many benefits in terms of power efficiency and compact design, it has some trade-offs in terms of performance efficiency. She says her team is looking to improve performance efficiency in the future by exploring innovative techniques to parallelize computations.

As well, the researchers tested RISE by using a hardware simulator in this study. Next, they will test RISE via a more complete hardware setup. Nevertheless, the team is excited about these initial results.

“The development of these prototypes marks a crucial step in transforming our theoretical concepts into tangible, functional devices,” says Azad. “By bringing our design to life in the form of an actual hardware chip, we aim to demonstrate its robustness and adaptability in diverse edge-computing scenarios and to ensure that our innovations make a meaningful impact in the real world.”

Source: IEEE Semiconductors